Some of the old school analog computation people were really into this idea. They visualized computations as wires and nodes. I remember one mechanical engineering professor, who was a big fan of nomograms. He wanted a set of networkable blocks so he could build a computer program on his desk top and have it run digitally. We could probably do this today, but few people are used to thinking about algorithms that way anymore, despite the inherent parallellism that such thinking requires. This was back in the early 1970s, so this idea has old roots.

Rather, a good idea frequently exposes yet another bottleneck that was hidden before.

Yes, but that isn’t a matter of complaint as such.

When you say that DRAMs are substantially slower, don’t you mean that large memory space and subsequent deep data channels are the problems? I’m not sure how to tackle that one though – it seems as least as hard a problem to break down as the serial-to-parallel challenge is.

Given that before the FPGA gets programmed, enough statistics have to be collected by the profiling unit to determine if it’s worthwhile, it’ll only be reprogrammed if it’s worth it. This is (roughly) the scheme used for Just-In-Time compilation for CPU emulation, and it works there.

–jt

But such automatic compilation of designs has been the “holy grail” of not just the FPGA world, but the entire parallel/scientific computing field for 40 years. It’s just really hard to extract more than a few way parallelism from non-trivial problems that are stated serially, even without the memory bottleneck. And it’s hard as hades for most humans to express parallel algorithms as such.

There has been a LOT of work done here, and every high-level or automatic design compiler I’ve seen makes a major tradeoff in either flexibility, performance, ease of use.

Usually, you can only pick one (or at most 2).
(e.g. Mitrionics, which focuses on ease-of-use,Handel-C which goes for flexibility, Viva, which is pretty good trades flexibility for a decent enough performance and )

The trouble I see here is in the target audience– if you have a major scientific computation to perform that can be accelerated with FPGAs, why would you use this custom processor, when for a little more effort you can get an FPGA designer who can make a custom design which will probably outperform this guy. If you have a webserver with many trivially parallel tasks, unless they map to what the desing compiler wants to see, you’ve wasted your silicon– it probably makes sense to buy another COTS box ‘o processors.

You’re spending a lot of silicon on a design tool that you’ll need once in a while– don’t get me wrong, it’s very cool to have it on a chip, and it’s a step towards “evolvable, self-programming hardware”, but I’m not sure of the practicality.

Bioinformatics & network security is one place where this might do very well. You have lots of string and pattern matching which avoids floating point (which currently kills FPGAs), very regular memory accesses and very simple operations (counters, comparators and address generators). But agian, the simplicity of the app makes me question whether it isn’t worth the designer time vs. this automatic solution.

–jt

In other words, its main achievement is to change the economics of speeding up programs using RC, because it shifts the weight of coding the reconfiguration from the application developer (who is human, and thus very expensive) to the CPU (which is silicon and very very cheap, albeit of course much less capable then the human)

Or am I misreading this?

I think that this chip lives on as VIA EDEN, but I don’t know if it still features the software translation that was the main feature of the transmeta chip. If I remember, VIA EDEN is featured as producing low power consumption (and of course not much heat).

In any case, yeah, this seems to be a new algorithm based on an old idea. I first heard about this sort of thing with Starbridge Systems about eight years ago or so:
http://www.starbridgesystems.com/

What seems interesting about this FPGA idea, to me, is that it seems like they are attempting to use an FPGA to speed up general processing, without reprogramming. Now, this sort of thing rarely speeds up programming by a significant portion, but given how challenging it is to make new, faster processors, this sounds like an excellent idea to improve performance of general-purpose processors a few percent more.

ILP (instruction-level parallelism) is a related idea, and also an old one. Even in the PC world, the original Pentium processor introduced a “superscalar” architecture, which meant that it can occasionally execute two instructions at a single cycle. Still, today’s monster chips don’t have a hundred instructions running parallel, and not because we don’t have enough chip space to do that. Program codes have inherent interdependency, which limits the amount of things you can do at a time… unless you find really really clever tricks.

There’s also the memory bottleneck issue. Modern DRAMs are usually hundreds of times slower than the CPU, which means the CPU often sits idle for hundreds of cycles just waiting for data. If the CPU suddenly becomes 1000x faster, the situation just becomes much worse (relatively speaking), unless we can redesign the code in a special way such that it does a LOT of computation with only a SMALL amount of data. (It could be feasible for some science applications, but impossible/impractical for most end-user applications.)

Wow, I can’t believe I just wrote an informative reply to Cosmic Variance! *giggle*

Speaking of wet dreams, I’m just reading an article on cloud processing, among other background referring to the modular and minimal Xios/3 OS based on xml. Everything on scalable internet, and internet on everything modular. (And Google ogling the proceeds which is both promising and scary.) Keep your fingers crossed for survival in the hard world of software.

A Xilinx Virtex-5 FPGA has as many as 51,840 slices, which, if it was all devoted to arithmetic would give 207,360 single bit adders or 25,920 8-bit adders. They run at 550 MHz, so the theoretical maximum for 8-bit addition is 14,256 billion operations per second.

Actual ratios depend on the operation. Generally, the CPU will have advantages at complicated operations like floating point, especially multiplication and addition, while the FPGA will be blindingly fast on simple 1-bit wide logic operations on as many as 4 variables. Such a logic operation could be, for example, ((A or B) and (C or D)) or ((not A) and (not B)), that is, any logic function of four variables.

FPGAs are widely used in experimental particle physics.